Many memory designs commonly use a column multiplexing structure to achieve a compact area. For high speed memory designs, e.g., in the Giga Hertz (Ghz) range, however, multiplexers having a large number N of inputs in some approaches increase the output delay (e.g., the slew rate) because of the heavy load when the N sub circuits in the multiplexers corresponding to the N number of inputs are coupled together. In some conditions, the N sub circuits coupled together also cause high leakage current.
Like reference symbols in the various drawings indicate like elements.